1. Field of the Invention
The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for tracking thermal mini-cycle stress over the life of an assembly.
2. Background of the Invention
As computer and other electronic systems have increased performance over time, the power consumed to enable the performance has increased dramatically. Up until recently power management has mostly been a reliability issue associated with the max temperatures components or subassemblies may experience. However, recently the absolute magnitude of the energy consumed in the operation of these systems, especially in large data centers, has prompted the generation of a Standard Performance Evaluation Corporation power (SPECpower™) benchmark. This benchmark is an assessment mechanism to ensure that such systems are designed to minimize energy consumption by significantly reducing the power consumed during those periods in which little productivity is asked of the system.
A system behavior which requires significant power during periods of high production, but requires very little power consumption during idle or low production periods, will tend to experience large variations in temperature depending upon the nature of the thermal cooling paths and the work load demands on the system. These temperature variations may cause failures due to mechanical stress and strain induced fatigue for structures that are composed of materials with varying coefficients of thermal expansion (CTE). Too many thermal cycles of too high a magnitude may result in such failures. In a modern computer system the first level packaging, especially that using organic laminate carrier technology as a carrier for a relatively large silicon die with the processor circuits, has just such large CTE mismatch between carrier and die. In some game applications the organic carrier modules have been shown to be limited to ˜10K thermal cycles resulting from power on and off of those modules in application conditions. Exceeding those thermal cycle counts for those temperature excursions will result in either destruction of the thermal interface between the backside of the die and the facing face of the module lid, the back end of line (BEOL) of the chip that includes the metallization and dielectric material that interconnects the transistors and other circuit elements that make up the die, or even the C4 solder attach interface electrically connecting the die circuits to the carrier circuits.
Variations in size of the die, the thermal interface and underfill materials, the make up of the organic carrier and module lid, the second level attach method to the carrier circuit card, the temperature excursion magnitude have been shown to influence the number of thermal cycles that an assembly can withstand before significant deterioration is detectable. In other applications, such as a large processor die on an organic package, the total power on/off cycles which result in thermal cycles of 60° Celsius or more will cause end of life CTE mismatch induced fatigue failures after ˜1250 cycles. Lower magnitude thermal cycles on the order of 20° Celsius will allow many more cycles (>40000 over a 40000 power on hour assembly life).